--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:34:12 10/07/2013
-- Design Name:   
-- Module Name:   C:/Users/Ling Chun Kai/Documents/NUS modules/CG3207/Lab/CG3207/main_alu_test.vhd
-- Project Name:  LAB2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: alu
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY main_alu_test IS
END main_alu_test;
 
ARCHITECTURE behavior OF main_alu_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT alu
    PORT(
         Clk : IN  std_logic;
         Control : IN  std_logic_vector(5 downto 0);
         Operand1 : IN  std_logic_vector(31 downto 0);
         Operand2 : IN  std_logic_vector(31 downto 0);
         Result1 : OUT  std_logic_vector(31 downto 0);
         Result2 : OUT  std_logic_vector(31 downto 0);
         Debug : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal Control : std_logic_vector(5 downto 0) := (others => '0');
   signal Operand1 : std_logic_vector(31 downto 0) := (others => '0');
   signal Operand2 : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal Result1 : std_logic_vector(31 downto 0);
   signal Result2 : std_logic_vector(31 downto 0);
   signal Debug : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: alu PORT MAP (
          Clk => Clk,
          Control => Control,
          Operand1 => Operand1,
          Operand2 => Operand2,
          Result1 => Result1,
          Result2 => Result2,
          Debug => Debug
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;

      -- insert stimulus here 
		--- MULTIPLY---, expect FF...1
		operand1 <= X"FFFFFFFF";
		operand2 <= X"FFFFFFFF";
		control <= "011000"; -- multiply unsigned
		
		wait for CLK_PERIOD * 5;
		
		--- MULTIPLY---, expect 15E6F55DD4321544h
		operand1 <= X"7FFFFFFF";
		operand2 <= X"2BCDEABC";
		control <= "011001"; -- multiply signed
		
		wait for CLK_PERIOD * 5;
		
		--- MULTIPLY---, expect 0000.....1h
		operand1 <= X"FFFFFFFF";
		operand2 <= X"FFFFFFFF";
		control <= "011001"; -- multiply signed
		
		wait for CLK_PERIOD * 5;
		
		--- NOP ---, expect nothing...
		operand1 <= X"ABCDEFAB";
		operand2 <= X"CAFEBABE";
		control <= "000000"; 
		
		wait for CLK_PERIOD * 1;
		
		--- MULTIPLY---, expect FB7F3A12F918BA84h
		operand1 <= X"FFAFFFAF";
		operand2 <= X"FBCDEABC";
		control <= "011000"; -- multiply usigned
		
		wait for CLK_PERIOD * 5;
		
		--- DIVIDE ---, expect Q9, Remainder 7F6E573
		operand1 <= X"ABCDEFAB";
		operand2 <= X"12345678";
		control <= "011100"; -- divide unsigned
		
		wait for CLK_PERIOD * 18;
		
		--- NOP --- TEST IF MESSUP DIVIDE
		operand1 <= X"00000000";
		operand2 <= X"00000000";
		control <= "000000";
		
		wait for CLK_PERIOD * 1;
		
		--- DIVIDE ---, 
		operand1 <= X"FBCDEFAB";
		operand2 <= X"12345678";
		control <= "011101"; -- divide signed
		
		wait for clk_period * 18;
		
		--- NOP --- TEST IF MESSUP DIVIDE
		operand1 <= X"00000000";
		operand2 <= X"00000000";
		control <= "000000";
		
		wait for clk_period * 1;
		
		--- ADDITION ---, expect 
		operand1 <= X"ABCDEFAB";
		operand2 <= X"CAFEBABE";
		control <= "001001"; -- Addition signed
		
		wait for CLK_PERIOD * 1;
		
		--- SUBTRACTION ---
		operand1 <= X"ABCDEFAB";
		operand2 <= X"CAFEBABE";
		control <= "001101"; -- Subtraction signed
		
		wait for CLK_PERIOD * 1;
		
		--- SHIFTER ---
		operand1 <= X"12345676";
		operand2 <= X"00000005";
		control <= "010100";
		
		wait for CLK_PERIOD * 1;
		
		-- SLT ---
		operand1 <= X"72345677"; -- no, not less than, otput 0
		operand2 <= X"00000005";
		control <= "001111";
		
		wait for CLK_PERIOD * 1;
		
		operand1 <= X"82345677"; -- yes, less than outout 1
		operand2 <= X"00000005";
		control <= "001111";
		
		wait for CLK_PERIOD * 1;
		
		-- BEQ --
		operand1 <= X"82345677"; -- nope
		operand2 <= X"00000005";
		control <= "000101";
		
		wait for CLK_PERIOD * 1;
		
		operand1 <= X"00000005"; -- yup
		operand2 <= X"00000005";
		control <= "000101";
		
		wait for CLK_PERIOD * 1;
		
		-- BEQ --
		operand1 <= X"82345677"; -- yup
		operand2 <= X"00000005";
		control <= "000110";
		
		wait for CLK_PERIOD * 1;
		
		operand1 <= X"00000005"; -- nop
		operand2 <= X"00000005";
		control <= "000110";
		
		wait for CLK_PERIOD * 1;
		
		-- DIV --
		operand1 <= X"80000000"; -- 
		operand2 <= X"FFFFFFFF"; -- KABOOM OVERFLOW when signed
		control <= "011101";
		
		wait for CLK_PERIOD * 18;
		
		operand1 <= X"80000000"; -- 
		operand2 <= X"00000001"; -- but no overflow when unsigned!
		control <= "011100";
		
		wait for CLK_PERIOD * 18;
		
		-- no overflow here either
		operand1 <= X"80000000"; -- 
		operand2 <= X"FFFFFFFF"; -- but no overflow when unsigned!
		control <= "011100";
		
		wait for CLK_PERIOD * 18;
		
		--- NOP --- TEST IF MESSUP DIVIDE
		operand1 <= X"00000000";
		operand2 <= X"00000000";
		control <= "000000";
		
      wait;
   end process;

END;
